1. Field of the Invention
The present invention relates to an error correcting apparatus and method of a digital processing system, and more particularly, to an apparatus and method which can simultaneously correct both an erasure error and a general error.
2. Description of the Related Art
In a digital data transmitting system, data to be transmitted is modulated and coded. In a digital data receiving system, data to be received is demodulated and decoded. A digital data recording/reproducing system modulates and codes data so as to be recorded in a recording medium, and demodulates and decodes the modulated and coded data so as to reproduce the recorded data. Hereinafter, the digital recording/reproducing system will be explained as an example of a digital processing system.
When reproducing the recorded data in the digital recording/reproducing system, an error data which may be generated during a decoding process should be corrected to accurately reproduce the data. FIG. 1 is a block diagram illustrating a signal processing flow for reproducing the recorded data in the digital recording/reproducing system.
Referring to FIG. 1, a head 111 designates a recording/reproducing head of a channel A, and a head 131 indicates a recording/reproducing head of a channel B. Elements 111-122 for reproducing the recorded data by accessing data of the channel A have the same form as elements 131-142, respectively, for reproducing the recorded data by accessing data of the channel B. For convenience, a description will be given on the basis of a path reproducing the recorded data through the channel A only. The head 111 of the channel A reads data from the recording medium. An amplifier 112 amplifies a signal read from the head 111. A PLL (Phase Lock Loop) 113 reproduces a clock from the amplified signal and supplies the reproduced clock to a demodulator 114 together with data. The demodulator 114 converts received serial data into parallel data and demodulates data modulated when recorded to 8-bit original data. A synchronous detector 116 detects a synchronizing signal from successive data streams of the parallel data. A C2 decoder 117 and a C1 decoder 118, which form part of an error correcting unit, correct error data of received data according to the detected synchronizing signal generated from the synchronous detector 116. There are two kinds of error data, namely, firstly, an erasure error of which error position can be determined by its associated error flag, and secondly, a general error without any flag provided, thereby being incapable of determining its error position. The operation of the C2 decoder 117 and the C1 decoder 118 will be described later on with reference to FIG. 2. A CRC (Cyclic Redundancy Code) part 119 confirms whether the error data is normally corrected through the C2 decoder 117 and the C1 decoder 118. A TBC (Time Base Correction) part 120 eliminates a jitter contained in data generated from the CRC part 119. A deshuffling part 121 re-arranges data generated from the TBC part 120 to an original data format. A concealment part 122 converts data which does not correct error data from the re-arranged data into a value similar to original data so as not to be noticed by human beings. A multiplexer 151 multiplexes data generated from the concealment part 122 of the channel A and a concealment part 142 of the channel B. A digital-to-analog (D/A) converter 152 converts the multiplexed data into an analog signal. A low pass filter (LPF) 153 low pass filters the analog signal to a voice signal band.
FIG. 2 illustrates a conventional error correcting apparatus for implementing an error correcting function in FIG. 1. The error correcting function is performed by the elements 114-118 of the channel A and elements 134-138 of the channel B. The demodulator 114 receives the serial data reproduced from the head 111 of the channel A, converts the serial data into the 8-bit parallel data, and demodulates the data modulated when recorded to the original data. The demodulator 114 is constructed as shown in FIG. 3. It is assumed that a modulation code of data recorded in the recording medium uses an eight-to-sixteen modulation plus code for converting 8-bit data into 16-bit data. Referring to FIG. 3, a serial/parallel converter 311 receives the serial data reproduced by a serial clock S.sub.-- CLK and converts data received by a parallel clock P.sub.-- CLK into the 8-bit parallel data. A memory controller 311 receives the 8-bit parallel data generated from the serial/parallel converter 311, re-arranges the 8-bit parallel data to 16-bit parallel data, and generates a memory read enable signal synchronized with the 16-bit parallel data. A ROM (Read Only Memory) 313 includes a demodulation data table and receives the 16-bit data generated from the memory controller 312 as an address. In this case, since 2.sup.8 code words among 2.sup.16 code words are used, 2.sup.8 correct conversion data is stored in the demodulation data table of the ROM 313, and "00" or "FF" is stored in the remaining regions of the demodulation data table. The ROM 313 receives the 16-bit data generated from the memory controller 312 as the address and is activated when the memory read enable signal is generated from the memory controller 312, thereby reading data stored in a corresponding address. A latch 314 latches demodulation data generated from the ROM 313 by the parallel clock P.sub.-- CLK and supplies the latched demodulation data to the synchronous detector 116. Therefore, the demodulator 114 demodulates 16-bit modulation data reproduced from the recording medium to the original 8-bit data.
The synchronous detector 116 detects synchronizing data of the demodulation data generated from the demodulator 114 and generates the detected synchronizing data. The C2 decoder 117 corrects a general error from the detected synchronizing data. If the C2 decoder cannot, and therefore, does not correct the general error in the detected synchronizing data, the C2 decoder 117 generates a corresponding erasure error and an error flag. The C1 decoder 118 receives an output of the C2 decoder 117 and generates final corrected data by correcting both general errors and erasure errors. The C2 decoder 117 and the C1 decoder 118 may use AHA4310, AHA4510, AHA4810 or AHA4010 devices, which are Reed-Solomon ECC coprocessor ICs, manufactured by Advanced Hardware Architectures Co.
In operation, data which is converted into a digital form and then recorded/reproduced or transmitted may have some type of error by external influence during its processing. To correct the error data of the received data, an error correcting code (ECC) is generally used. A "general error" means error data without any error flag provided, thereby making it not possible to determine its error position. An "erasure error" means error data of which error position can be determined by its associated error flag. It is assumed that a C1 code and a C2 code are used as the error correcting codes. The error correcting codes currently used in most digital recording/reproducing apparatuses are Reed-Solomon codes. In the digital processing system using the Reed-Solomon codes, an error correcting function is carried out by a unit of a block code as shown in FIG. 4. That is, when decoding the demodulation data by the unit of a block code, the C2 decoder 117 corrects the error data of received data by the row unit of a block code. The C1 decoder 118 corrects the error data of received data by the column unit of a block code. Namely, when correcting the error data, received data and the C2 code are analyzed by the row unit, and then the received data and C1 code are analyzed by the column unit.
Data is converted into source data according to the channel in the demodulator 114. The converted data stream is supplied to the C2 decoder 117 to correct a general error generated at the interior of the data stream. The C2 decoder 117 corrects the error by carrying out a decoding operation. If there is no general error within one code or if there is a general error which can be corrected, the C2 decoder 117 corrects the general error and generates error corrected data. If there is a general error which can not be corrected, the C2 decoder 117 supplies the error flag to the C1 decoder 118 together with the original data. The C1 decoder 118 performs the decoding operation on the original data with the general error and the erasure error by using the original data and the error flag generated from the C2 decoder 117. Generally, the Reed-Solomon code can correct the general error by 1/2 of additional information and correct the erasure error by the length of the additional information.
Typically, the type of error generated when the digital data is transmitted or recorded/reproduced has two types. One is a random error and the other is a burst error generating errors successively. To effectively correct these errors, a block code or a product code is used. In the above examples, it is assumed that the C1 code or the C2 code is used. The conventional error correcting apparatus of FIG. 2 corrects the general error in the C2 code of the block code shown in FIG. 4 and corrects the general error and the erasure error in the C1 code. When there is error data among data reproduced from the demodulator 114, if there is no conversion data corresponding to the data having the error in the demodulation data table of the ROM 313, "00" or "FF" is generated. However, the error flag indicating that there is error data is not generated from the demodulator 114. Therefore, the C2 decoder 17 does not receive the error flag from the demodulator 114, and thus it can not correct the erasure error. As noted above, the Reed-Solomon code corrects the general error by 1/2 of the additional information and corrects the erasure error by the length of the additional information. The additional information of the C2 code is 10 bytes and that of the C1 code is 16 bytes as indicated in FIG. 4. Therefore, if the C2 decoder 117 corrects only the general error and the C1 decoder 118 corrects the general error and the erasure error, the amount of errors per block which can be corrected is C2=5.times.208=1040 bytes and C1=16.times.172=2752 bytes. However, the C2 decoder 117 and the C1 decoder 118 can correct both the general error and the erasure error. In the conventional error correcting apparatus, the burst error is corrected in the second code. If the erasure error can be corrected even in the first code, the error correcting capability will be greatly improved.